In the manufacture of CMOS (complementary insulation gate type) integrated circuits, more concretely in the formation of CMOS-FET (electric field effect transistor) on the semiconductor substrate, it is indispensable to form an extremely thin diffused layer of a source region and a drain region of FET in order to restrict short channel effect that will become conspicuous along with microstructure for high integration and high speed. As a consequence, the diffused layer of the source region and the drain region becomes highly resistant, causing the deterioration in transistor driving power and the increase of delay time.
To solve the above problems, technologies to make the diffused layer resistance low by forming a metallic layer on the diffused layer of the source region and the drain region have been proposed heretofore, one of which is so called Salicide process.
One example of Salicide process is explained hereinafter in reference to FIGS. 1(a) and (b).
In FIG. 1(a), a separation region 51 is formed on a semiconductor substrate 50, and a gate electrode 53 (generally polysilicon) is formed via a gate insulating film 52 on the partial surface of the element region separated by the above separation region 51, and further nitrided silicon (SiN) 54 film is formed on a side-wall insulation layer of the above gate electrode 53.
In the next place, a diffused layer 55 of source region and drain region is formed by the ion implantation method well known to those skilled in the art, a Ti target is sputtered by use of Ar plasma, thereby Ti film 56 is accumulated.
Further, a cap film comprising nitrided titanium (TiN) film 57 is formed so as to restrict the roughness of titanium silicide surface at the formation of titanium silicide described later. At this moment, normally, titanium target is sputtered by use of plasma of mixture gas of argon and nitrogen, thereby nitriding reaction of titanium is induced on the titanium-target surface, and TiN film 57 is accumulated on the abovementioned Ti film 56.
Heat treatment is carried out on the multi layer film formed as shown above, under nitrogenous atmosphere, and as shown in FIG. 1(b), titanium silicide (TiSi.sub.2) film 58a and 58b are formed by solid phase reaction of titanium in the TiN film 56 and silicon in the diffused layer 55 and silicon in the gate electrode 53. Then TiN film 57 and unreacted Ti film 56 are removed by etching by use of mixture solution of sulfuric acid and hydrogen peroxide.
According to the above process, self aligned metal layers, i.e., TiSi.sub.2 film 58a and 58b can be formed only on the diffused layer 55 and the gate electrode 53. By the way, after this, insulating film is accumulated on the whole surface, a contact ball is formed, and wiring line is arranged so as to connect TiSi.sub.2 films 58a and 58b.
TiSi.sub.2 films 58a and 58b formed in the above manner reduce the sheet resistance at the region of the diffused layer 55 and the gate electrode 53, for example, the formation of TiSi.sub.2 film 58a with film thickness 80 nm reduces the sheet resistance of the diffused layer 55 with juncton depth 250 nm from 50 .OMEGA./.quadrature. to 3 .OMEGA./.quadrature..
On the other hand, in the silicon MOSFET as mentioned above, it is indispensable to form an extremely thin diffused layer of a source region and a drain region in order to restrict short channel affect that will become conspicuous along with microstructure for high integration and high speed. As a result, there is a tendency where the clearance between the interface of PN junction of the diffused layer 55 and the interface of substrate silicon of TiSi.sub.2 film 58a will become small. And it has been found that the small clearance causes the juncton leak current of PN juncton of the diffused layer 55 to become conspicuous.
To avoid this phenomenon, it has become necessary to make thin film thickness of TiSi.sub.2 film 58a as well as the depth of the diffused layer in accordance with Scale rule, further, it has become necessary make a thin width of the source region and the drain region-electrode in accordance with scale rule from the viewpoint of reduction of juncton capacity.
However, in the case using the thin silicide film as mentioned above, it has been found that there will be the following problems (1) and (2), becoming large factors to prevent microstructure that is indispensable for high integration and high speed of elements.
(1) The rise of the specific resistance of TiSi.sub.2 itself was observed by making the TiSi.sub.2 film thin. In concrete, it was found that when TiSi.sub.2 58a was formed in thickness 55 nm on the diffused layer 55 with as rather shallow a juncton depth as 180 nm, and than formed by Rapid Thermal Annealing (RTA) for 30 seconds at 750.degree. C. and for 30 seconds at 850.degree. C., the specific resistance of TiSi.sub.2 58a showing 13 .mu..OMEGA.cm increased by 30% in bulk TiSi.sub.2, becoming a large factor to prevent the realization of microstructure of elements. This phenomenon becomes more conspicuous as TiSi.sub.2 film is made thinner, for instance, in the case when TiSi.sub.2 58a with film thickness 30 nm is formed on the diffused layer 55 with as rather shallow a juncton depth as 180 nm, the specific resistance increases by about 100%. The above is a problem owing to the reduction of TiSi.sub.2 in its film thickness direction. PA1 (2) It has been found that the electrode sheet resistance increases abnormally as FET is made into microstructure in accordance with scale rule and the width of gate and source and drain electrode becomes narrow. For instance, in the case when TiSi.sub.2 58a with film thickness 55 nm is attached to source and drain electrode with thickness lam, the sheet resistance appears 3 .OMEGA./.quadrature., while in the when TiSi.sub.2 58a with film thickness 55 nm is attached to source and drain electrode with thickness 1 .mu.m, the sheet resistance becomes 12 .OMEGA./.quadrature..
And the increase of the sheet resistance of TiSi.sub.2 in such a micro fine shape becomes more conspicuous as the thickness of TiSi.sub.2 gets thinner, for instance, when the thickness of TiSi.sub.2 58a is 30 nm, the sheet resistance of source and drain electrode of 2 .mu.m is 40 .OMEGA./.quadrature., while the sheet resistance becomes 2 .OMEGA./.quadrature. in source and drain electrode of 5 .mu.m.
The main possible cause for the increase in resistance mentioned above may be understood as shown below. In the case where the region of the reaction portion between titanium in Ti film 56 and silicon in the diffused layer 55 is a micro fine shape, the contribution of the surface to unit mass naturally increases, and interface energy affects largely upon mophology, i.e., TiSi.sub.2 will easily aggregate in order to reduce interface energy.
As a result, for example, as shown in FIG. 2, TiSi.sub.2 58a in the diffused layer 55 becomes partially thinner or gets into island shape, therefore, it has been impossible to realize desired low resistance.
As mentioned heretofore, in the formation of CMOSFET in prior art, there has been a problem that when salicide process was adopted to make electrode portion react with transition metal and make it into metal with low resistance in order to prevent the increase of incidental resistance accompanying with microstructure, if the region of the reaction portion was of a micro fine shape, transition metal chemical aggregated owing to heat process and resistance increased, therefore, it was impossible to realize a desired low resistance.
The above discussion is also true of the silicide process adopted to make the resistance of bipolar base electrode low.